MOS Technology 6502
From Misc Data Digs
Revision Differences[edit | edit source]
The opcode ROR is broken on pre-June 1976 CPUs, as the carry flag is not updated, it shifts left rather than right, and a 0 is shifted in rather than the carry flag.
(Source: Page Table)
Undocumented Opcodes[edit | edit source]
KIL/JAM[edit | edit source]
Every opcode that is 0x?2 except for 0x82, 0xA2, 0xC2, and 0xE2, locks up the CPU. The only way to unlock it is to reset the CPU.
SLO/ASO[edit | edit source]
Opcodes 0x03, 0x07, 0x0F, 0x13, 0x17, 0x1B, and 0x1F combines the ORA and ASL instructions. It shifts left one bit in memory, then ORs register A in memory.
RLA[edit | edit source]
Opcodes 0x23, 0x27, 0x2F, 0x33, 0x37, 0x3B, and 0x3F combines the ROL and RLA instructions. It rotates left one bit in memory, then ANDs register A with memory.
SRE/LSE[edit | edit source]
Opcodes 0x43, 0x47, 0x4F, 0x53, 0x57, 0x5B, and 0x5F combines the EOR and LSR instructions. It shifts right one bit in memory, then EORs register A with memory.
RRA[edit | edit source]
Opcodes 0x63, 0x67, 0x6F, 0x73, 0x77, 0x7B, and 0x7F combines the ROR and ADC instructions. It rotates right one bit in memory, then ANDs register A with memory (with carry).
RRA[edit | edit source]
Opcodes 0x63, 0x67, 0x6F, 0x73, 0x77, 0x7B, and 0x7F combines the ROR and ADC instructions. It rotates right one bit in memory, then ANDs register A with memory (with carry).
SAX/AXS/AAX[edit | edit source]
Opcodes 0x83, 0x87, 0x8F, and 0x97 combines the STA and STX instructions. It ANDs the A and X registers, with neither register changed, are stores these in memory.
LAX[edit | edit source]
Opcodes 0xA3, 0xA7, 0xAF, 0xB3, 0xB7, and 0xBF combines the LDA and LDX instructions. Predictably, it loads one value in a memory location into both the A and X registers. LAX Immediate does not have an opcode as that is affected by line noise on the data bus.
DCP/DCM[edit | edit source]
Opcodes 0xC3, 0xC7, 0xCF, 0xD3, 0xD7, 0xDB, and 0xDF combines the CMP and DEC instructions. It decrements a memory location's value and compares it the A register.
ISB/ISC/INS[edit | edit source]
Opcodes 0xE3, 0xE7, 0xEF, 0xF3, 0xF7, 0xFB, and 0xFF combines the SBC and INC instructions. The memory location is incremented, then subrtacts memory from accumulator.
ANC[edit | edit source]
Opcodes 0x0B and 0x2B ANDs register A with a value, then moves bit 7 of A into the carry flag.
ALR/ASR[edit | edit source]
Opcodes 0x4B ANDs register A with a value, then shifts right logically.
ARR[edit | edit source]
Opcodes 0x6B ANDs an immediate value, then RORs register A. However, the carry flag is bit 6 and the overflow flag is bit 6 xor bit 5.
(Source: No More Secrets by groepaz)